An Efficient Full Search Block Motion Estimation using Trace and Sum of Off- Diagonal based Match and FPGA Implementation

The H. 264/AVC offer many coding tools that give higher compression ratio compared to earlier standards. These tools increase the computational complexity of the motion estimation. In this paper, we have presented a computationally efficient method to speed up the search process by minimizing the computational load on general full search. The proposed method is having two phases, wherein the first phase involves search for the nearly matching block using the trace and sum of off-diagonal elements. Only upon match, the Sum of Absolute Differences (SAD)is calculated for best motion prediction in the second phase and it is only for limited number of blocks. The trace and off-diagonal sum matching requires O(2n) computations and O(n2) computations are required in case of full search. Hence, the proposed method reduces 75% to 80% of SAD computations of full search motion estimation. This leads to significant improvement in coding efficiency compared to the existing motion estimation techniques without much degradation in video quality. FPGA implementation result shows that, the design can work at the maximum clock frequency of 420 MHz with the power consumption of 34. 86mW